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Datasheet File OCR Text:

ST72101/ST72212/ST72213
8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
DATASHEET
s
s
s s
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s s s s s s
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User Program Memory (ROM/OTP/EPROM): 4 to 8K bytes Data RAM: 256 bytes, including 64 bytes of stack Master Reset and Power-On Reset Run, Wait, Slow, Halt and RAM Retention modes 22 multifunctional bidirectional I/O lines: - 22 programmable interrupt inputs - 8 high sink outputs - 6 analog alternate inputs - 10 to 14 alternate functions - EMI filtering Programmable watchdog (WDG) One or two 16-bit Timers, each featuring: - 2 Input Captures - 2 Output Compares - External Clock input (on Timer A only) - PWM and Pulse Generator modes Synchronous Serial Peripheral Interface (SPI) 8-bit Analog-to-Digital converter (6 channels) (ST72212 and ST72213 only) 8-bit Data Manipulation 63 Basic Instructions 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Complete Development Support on PC/DOSWINDOWSTM Real-Time Emulator Full Software Package on DOS/WINDOWSTM (C-Compiler, Cross-Assembler, Debugger)
PSDIP32
CSDIP32W
SO28
(See ordering information at the end of datasheet)
Device Summary
Features Program Memory- bytes RAM (stack) - bytes 16-bit Timers ADC Other Peripherals Operating Supply CPU Frequency Temperature Range Package May 2001 ST72101G1 4K one no ST72101G2 8K 256 (64) one no one yes two yes ST72213G1 4K ST72212G2 8K
Watchdog, SPI 3 to 5.5 V 8MHz max (16MHz oscillator) - 4MHz max over 85C - 40C to + 125C SO28 - SDIP32
Rev. 1.8
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Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 17 18 18
4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 22 23
5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 5.3.2 5.3.3 5.3.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 25 28 30 30 30 31 31 31 31 32 32 32 32 44
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Table of Contents
5.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 44 45 50 50 50 50 52 59 59 60 63 63 63 64 64 64 65 66 66 67 67 67 67 67 68 68 69
7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.4 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.6 A/D CONVERTER CHARACTERISTICS (ST72212 AND ST72213 ONLY) . . . . . . . . . . . 76 7.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.3.1 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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ST72101/ST72212/ST72213
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST72101, ST72213 and ST72212 HCMOS Microcontroller Units are members of the ST7 family. These devices are based on an industrystandard 8-bit core and feature an enhanced instruction set. They normally operate at a 16MHz oscillator frequency. Under software control, the ST72101, ST72213 and ST72212 may be placed in either WAIT, SLOW or HALT modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST72101, ST72213 and ST72212 feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes on the whole memory. The devices include an on-chip oscillator, CPU, program memory (ROM/OTP/EPROM versions), RAM, 22 I/O lines and the following on-chip peripherals: Analog-toDigital Converter (ADC) with 6 multiplexed analog inputs (ST72212 and ST72213 only), industry standard synchronous SPI serial interface, digital Watchdog, one or two independent 16-bit Timers, one featuring an External Clock Input, and both featuring Pulse Generator capabilities, 2 Input Captures and 2 Output Compares.
Figure 1. ST72101, ST72213 and ST72212 Block Diagram
OSCIN OSCOUT
Internal CLOCK OSC
PORT A SPI
PA0 -> PA7 (8 bits)
RESET
CONTROL PORT B 8-BIT CORE ALU
ADDRESS AND DATA BUS
PB0 -> PB7 (8 bits)
TIMER A PORT C 8-BIT ADC 1) TIMER B
2)
PROGRAM MEMORY (4 - 8K Bytes)
PC0 -> PC5 (6 bits)
RAM (256 Bytes) VDD VSS POWER SUPPLY
WATCHDOG
1) ST72213 and ST72212 only 2) ST72212 only
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ST72101/ST72212/ST72213
1.2 PIN DESCRIPTION Figure 2. ST72212 Pinout (SO28) Figure 5. ST72212 Pinout (SDIP32)
RESET RESET OSCIN OSCOUT SS/PB7 SCK/PB6 MISO/PB5 MOSI/PB4 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/OCMP2_B/PC4 AIN3/ICAP2_B/PC3
1) V
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD VSS TEST/VPP1) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/CLKOUT/AIN2
OSCIN OSCOUT SS/PB7 SCK/PB6 MISO/PB5 MOSI/PB4 NC NC OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/OCMP2_B/PC4 AIN3/ICAP2_B/PC3
1) V on EPROM/OTP only PP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD VSS TEST/VPP1) PA0 PA1 PA2 PA3 NC NC PA4 PA5 PA6 PA7 PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/CLKOUT/AIN2
PP (1) V
on EPROM/OTP only EPROM/OTP l
Figure 3. ST72213 Pinout (SO28)
Figure 6. ST72213 Pinout (SDIP32)
RESET OSCIN OSCOUT SS/PB7 SCK/PB6 MISO/PB5 MOSI/PB4 NC NC OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/PC4 AIN3/PC3
1) V on EPROM/OTP only PP
RESET OSCIN OSCOUT SS/PB7 SCK/PB6 MISO/PB5 MOSI/PB4 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/PC4 AIN3/PC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD VSS TEST/VPP 1) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0/AIN0 PC1/AIN1 PC2/CLKOUT/AIN2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD V SS TEST/VPP1) PA0 PA1 PA2 PA3 NC NC PA4 PA5 PA6 PA7 PC0/AIN0 PC1/AIN1 PC2/CLKOUT/AIN2
1) V on EPROM/OTP only PP
Figure 4. ST72101 Pinout (SO28)
Figure 7. ST72101 Pinout (SDIP32)
RESET OSCIN OSCOUT SS/PB7 SCK/PB6 MISO/PB5 MOSI/PB4 NC NC OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 EXTCLK_A/PC5 PC4 PC3
1) V PP
RESET OSCIN OSCOUT SS/PB7 SCK/PB6 MISO/PB5 MOSI/PB4 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 EXTCLK_A/PC5 PC4 PC3
1) V on EPROM/OTP only PP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD VSS TEST/VPP 1) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0 PC1 PC2/CLKOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD VSS TEST/VPP1) PA0 PA1 PA2 PA3 NC NC PA4 PA5 PA6 PA7 PC0 PC1 PC2/CLKOUT
on EPROM/OTP only
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ST72101/ST72212/ST72213
Table 1. ST72212 Pin Configuration
Pin n Pin n SDIP32 SO28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 22 23 24 25 26 27 28 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 Pin Name RESET OSCIN OSCOUT PB7/SS PB6/SCK PB5/MISO PB4/MOSI NC NC PB3/OCMP2_A PB2/ICAP2_A PB1/OCMP1_A PB0/ICAP1_A PC5/EXTCLK_A/AIN5 PC4/OCMP2_B/AIN4 PC3/ICAP2_B/AIN3 PC2/CLKOUT/AIN2 PC1/OCMP1_B/AIN1 PC0/ICAP1_B/AIN0 PA7 PA6 PA5 PA4 NC NC PA3 PA2 PA1 PA0 TEST/V PP(1) VSS VDD Type Description Remarks
I/O Bidirectional. Active low. Top priority non maskable interrupt. I O Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1
I/O Port B7 or SPI Slave Select (active low) I/O Port B6 or SPI Serial Clock I/O Port B5 or SPI Master In/ Slave Out Data I/O Port B4 or SPI Master Out / Slave In Data Not Connected Not Connected I/O Port B3 or TimerA Output Compare 2 I/O Port B2 or TimerA Input Capture 2 I/O Port B1 or TimerA Output Compare 1 I/O Port B0 or TimerA Input Capture 1
External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1
I/O Port C5 or TimerA Input Clock or ADC Analog Input 5 External Interrupt: EI1 I/O Port C4 or TimerB Output Compare 2 or ADC Analog Input 4 Port C3 or TimerB Input Capture 2 or ADC Analog I/O Input 3 Port C2 or Internal Clock Frequency Output or ADC I/O Analog Input 2. Clockout is driven by Bit 5 of the miscellaneous register. Port C1 or TimerB Output Compare 1 or ADC Analog I/O Input 1 Port C0 or TimerB Input Capture 1 or ADC Analog I/O Input 0 I/O Port A7, High Sink I/O Port A6, High Sink I/O Port A5, High Sink I/O Port A4, High Sink Not Connected Not Connected I/O Port A3, High Sink I/O Port A2, High Sink I/O Port A1, High Sink I/O Port A0, High Sink I/S S S External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0
Test mode pin (should be tied low in user mode). In the EPROM programming mode, this pin acts as the programming voltage input VPP. Ground Main power supply
Note 1: VPP on EPROM/OTP only
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Table 2. ST72213 Pin Configuration
Pin n Pin n SDIP32 SO28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 22 23 24 25 26 27 28 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 Pin Name RESET OSCIN OSCOUT PB7/SS PB6/SCK PB5/MISO PB4/MOSI NC NC PB3/OCMP2_A PB2/ICAP2_A PB1/OCMP1_A PB0/ICAP1_A PC5/EXTCLK_A/AIN5 PC4/AIN4 PC3/AIN3 PC2/CLKOUT/AIN2 PC1/AIN1 PC0/AIN0 PA7 PA6 PA5 PA4 NC NC PA3 PA2 PA1 PA0 TEST/VPP(1) VSS VDD I/O I/O I/O I/O I/S S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type I/O I O I/O I/O I/O I/O Description Remarks
Bidirectional. Active low. Top priority non maskable interrupt.
Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. Port B7 or SPI Slave Select (active low) Port B6 or SPI Serial Clock Port B5 or SPI Master In/ Slave Out Data Port B4 or SPI Master Out / Slave In Data Not Connected Not Connected Port B3 or TimerA Output Compare 2 Port B2 or TimerA Input Capture 2 Port B1 or TimerA Output Compare 1 Port B0 or TimerA Input Capture 1 Port C5 or TimerA Input Clock or ADC Analog Input 5 Port C4 or ADC Analog Input 4 Port C3 or ADC Analog Input 3 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1
Port C2 or Internal Clock Frequency Output or ADC Analog Input 2. Clockout is driven by Bit 5 External Interrupt: EI1 of the miscellaneous register. Port C1 or ADC Analog Input 1 Port C0 or ADC Analog Input 0 Port A7, High Sink Port A6, High Sink Port A5, High Sink Port A4, High Sink Not Connected Not Connected Port A3, High Sink Port A2, High Sink Port A1, High Sink Port A0, High Sink External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0
Test mode pin (should be tied low in user mode). In the EPROM programming mode, this pin acts as the programming voltage input VPP. Ground Main power supply
Note 1: VPP on EPROM/OTP only
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Table 3. ST72101 Pin Configuration
Pin n Pin n SDIP32 SO28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 22 23 24 25 26 27 28 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 Pin Name RESET OSCIN OSCOUT PB7/SS PB6/SCK PB5/MISO PB4/MOSI NC NC PB3/OCMP2_A PB2/ICAP2_A PB1/OCMP1_A PB0/ICAP1_A PC5/EXTCLK_A PC4 PC3 PC2/CLKOUT PC1 PC0 PA7 PA6 PA5 PA4 NC NC PA3 PA2 PA1 PA0 TEST/VPP(1) VSS VDD I/O I/O I/O I/O I/S S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type I/O I O I/O I/O I/O I/O Description Bidirectional. Active low. Top priority non maskable interrupt. Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator. Port B7 or SPI Slave Select (active low) Port B6 or SPI Serial Clock Port B5 or SPI Master In/ Slave Out Data Port B4 or SPI Master Out / Slave In Data Not Connected Not Connected Port B3 or TimerA Output Compare 2 Port B2 or TimerA Input Capture 2 Port B1 or TimerA Output Compare 1 Port B0 or TimerA Input Capture 1 Port C5 or TimerA Input Clock Port C4 Port C3 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI1 Remarks
Port C2 or Internal Clock Frequency Output. Clockout External Interrupt: EI1 is driven by MCO bit of the miscellaneous register. Port C1 Port C0 Port A7, High Sink Port A6, High Sink Port A5, High Sink Port A4, High Sink Not Connected Not Connected Port A3, High Sink Port A2, High Sink Port A1, High Sink Port A0, High Sink External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI1 External Interrupt: EI1 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0 External Interrupt: EI0
Test mode pin (should be tied low in user mode). In the EPROM programming mode, this pin acts as the programming voltage input VPP. Ground Main power supply
Note 1: VPP on EPROM/OTP only.
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1.3 EXTERNAL CONNECTIONS The following figure shows the recommended external connections for the device. The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode. The 10 nF and 0.1 F decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff. Figure 8. Recommended External Connections The external reset network is intended to protect the device against parasitic resets, especially in noisy environments. Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.
VPP VDD
10nF +
VDD
0.1F
VSS
VDD
4.7K 0.1F EXTERNAL RESET CIRCUIT 0.1F
RESET
See Clocks Section Or configure unused I/O ports by software as input with pull-up
OSCIN OSCOUT
VDD
10K
Unused I/O
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1.4 MEMORY MAP Figure 9. Memory Map
0000h
HW Registers (see Table 5)
007Fh 0080h
0080h
Short Addressing RAM (zero page)
00FFh 0100h
16-bit Addressing 256 Bytes RAM
017Fh 0180h 013Fh 0140h
RAM
64 Bytes Stack or 16-bit Addressing RAM Reserved
017Fh
DFFFh E000h
8K Bytes Program Memory
F000h
FFDFh FFE0h
4K Bytes Program Memory Interrupt & Reset Vectors (see Table 4)
FFFFh
Table 4. Interrupt Vector Map
Vector Address FFE0-FFE1h FFE2-FFE3h FFE4-FFE5h FFE6-FFE7h FFE8-FFE9h FFEA-FFEBh FFEC-FFEDh FFEE-FFEFh FFF0-FFF1h FFF2-FFF3h FFF4-FFF5h FFF6-FFF7h FFF8-FFF9h FFFA-FFFBh FFFC-FFFDh FFFE-FFFFh Description Not Used Not Used Not Used Not Used Not Used Not Used Not Used TIMER B Interrupt Vector (ST72212 only) Not Used TIMER A Interrupt Vector SPI Interrupt Vector Not Used External Interrupt Vector EI1 External Interrupt Vector EI0 TRAP (software) Interrupt Vector RESET Vector Remarks
Internal Interrupt Internal Interrupt Internal Interrupt External Interrupt External Interrupt CPU Interrupt
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Table 5. Hardware Register Memory Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh to 001Fh 0020h 0021h 0022h 0023h 0024h 0025h to 0030h 0031h 0032h 0033h 0034h-0035h 0036h-0037h 0038h-0039h 003Ah-003Bh 003Ch-003Dh 003Eh-003Fh Timer A TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR SPI WDG MISCR SPIDR SPICR SPISR WDGCR Port A PADR PADDR PAOR Port B PBDR PBDDR PBOR Block Name Port C Register Label PCDR PCDDR PCOR Register name Data Register Data Direction Register Option Register Reserved Area (1 Byte) Data Register Data Direction Register Option Register Reserved Area (1 Byte) Data Register Data Direction Register Option Register Reserved Area (21 Bytes) Miscellaneous Register Data I/O Register Control Register Status Register Watchdog Control register Reserved Area (12 Bytes) Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register Reserved Area (1 Byte) 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 00h xxh 0xh 00h 7Fh R/W R/W R/W Read Only R/W 00h 00h 00h R/W R/W R/W 00h 00h 00h R/W R/W R/W Reset Status 00h 00h 00h Remarks R/W R/W R/W
0040h
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Address 0041h 0042h 0043h 0044h-0045h 0046h-0047h 0048h-0049h 004Ah-004Bh 004Ch-004Dh 004Eh-004Fh 0050h to 006Fh 0070h 0071h 0072h to 007Fh
Block Name
Register Label TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR
Register name Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register Reserved Area (32 Bytes)
Reset Status 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h
Remarks R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W
Timer B 1)
ADC 2)
ADCDR ADCCSR
Data Register Control/Status Register Reserved Area (14 Bytes)
00h 00h
Read Only R/W
Notes: 1. ST72212 only, reserved area for other devices. 2. ST72212 and ST72213 only, reserved otherwise.
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES
s s s s s s s s
63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
2.3 CPU REGISTERS The 6 CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions. Figure 10. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable
Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh
15 0 7 0 1 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 11. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 11. Stack Manipulation Example
CALL Subroutine @ 0140h Interrupt Event PUSH Y POP Y IRET RET or RSP
SP SP CC A X PCH SP PCH @ 017Fh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Lower Address = 0140h Stack Higher Address = 017Fh
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3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES
3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC). The external Oscillator clock is first divided by 2, and division factor of 32 can be applied if Slow Mode is selected by setting the SMS bit in the Miscellaneous Register. This reduces the frequency of the fCPU; the clock signal is also routed to the on-chip peripherals. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for fosc. The circuit shown in Figure 13 is recommended when using a crystal, and Table 6 lists the recommended capacitance and feedback resistance values. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. Use of an external CMOS oscillator is recommended when crystals outside the specified frequency ranges are to be used. Table 6. Recommended Values for 16 MHz Crystal Resonator (C0<7pF)
RSMAX COSCIN COSCOUT 40 56pF 56pF 60 47pF 47pF 150 22pF 22pF
COSCIN COSCOUT
Figure 12. External Clock Source Connections
OSCIN
OSCOUT NC
EXTERNAL CLOCK
Figure 13. Crystal/Ceramic Resonator
OSCIN
OSCOUT
C0: parasitic shunt capacitance of the quartz crystal. RSMAX: equivalent serial resistor of the crystal (uper limit, see crystal specification). COSCOUT, COSCIN: maximum total capacitance on OSCIN and OSCOUT, including the external capacitance plus the parasitic capacitance of the board and the device.
Figure 14. Clock Prescaler Block Diagram
%2 OSCIN OSCOUT
% 16 fCPU to CPU and Peripherals
COSCIN
COSCOUT
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3.2 RESET 3.2.1 Introduction There are three sources of Reset: - RESET pin (external source) - Power-On Reset (Internal source) - WATCHDOG (Internal Source) The Reset Service Routine vector is located at address FFFEh-FFFFh. 3.2.2 External Reset The RESET pin is both an input and an open-drain output with integrated pull-up resistor. When one of the internal Reset sources is active, the Reset pin is driven low , for a duration of tRESET, to reset the whole application. 3.2.3 Reset Operation The duration of the Reset state is a minimum of 4096 internal CPU Clock cycles. During the Reset state, all I/Os take their reset value. A Reset signal originating from an external source must have a duration of at least tPULSE in order to be recognised. This detection is asynchronous and therefore the MCU can enter Reset state even in Halt mode. At the end of the Reset cycle, the MCU may be held in the Reset state by an External Reset signal. The RESET pin may thus be used to ensure VDD has risen to a point where the MCU can operate correctly before the user program is run. FolFigure 15. Reset Block Diagram lowing a Reset event, or after exiting Halt mode, a 4096 CPU Clock cycle delay period is initiated in order to allow the oscillator to stabilise and to ensure that recovery has taken place from the Reset state. In the high state, the RESET pin is connected internally to a pull-up resistor (RON). This resistor can be pulled low by external circuitry to reset the device. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to use the external connections shown in Figure 8. 3.2.4 Power-on Reset This circuit detects the ramping up of VDD, and generates a pulse that is used to reset the application (at approximately VDD= 2V). Power-On Reset is designed exclusively to cope with power-up conditions, and should not be used in order to attempt to detect a drop in the power supply voltage. Caution: to re-initialize the Power-On Reset, the power supply must fall below approximately 0.8V (Vtn), prior to rising above 2V. If this condition is not respected, on subsequent power-up the Reset pulse may not be generated. An external Reset pulse may be required to correctly reactivate the circuit.
INTERNAL RESET COUNTER POWER-ON RESET WATCHDOG RESET OSCILLATOR SIGNAL TO ST7 RESET RESET VDD
RON
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4 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 1. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - The I bit of the CC register is set to prevent additional interrupts. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 4.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 1. 4.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed and inverted before entering the edge/level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 4.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: - The I bit of the CC register is cleared. - The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: - Writing "0" to the corresponding bit in the status register or - Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) Figure 16. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTERRUPT PENDING? Y
FETCH NEXT INSTRUCTION
N
IRET? Y
STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
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Table 7. Interrupt Mapping
Source Block RESET TRAP EI0 EI1 Description Reset Software External Interrupt PA0:PA7 External Interrupt PB0:PB7, PC0:PC5 Not Used Transfer Complete Mode Fault Input Capture 1 Output Compare 1 Input Capture 2 Output Compare 2 Timer Overflow Not Used Input Capture 1 Output Compare 1 Input Capture 2 Output Compare 2 Timer Overflow Register Label N/A N/A N/A N/A Flag N/A N/A N/A N/A SPIF MODF ICF1_A OCF1_A ICF2_A OCF2_A TOF_A ICF1_B OCF1_B ICF2_B OCF2_B TOF_B Exit from HALT yes no yes yes Vector Address FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h Priority Order Highest Priority
SPI
SPISR
no
TIMER A
TASR
no
FFF2h-FFF3h
FFF0h-FFF1h
TIMER B 1)
TBSR
no
FFEEh-FFEFh
Not Used
FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
Lowest Priority
Note 1: Timer B is available on ST72212 only.
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4.4 POWER SAVING MODES 4.4.1 Introduction There are three Power Saving modes. Slow Mode is selected by setting the relevant bits in the Miscellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions. 4.4.2 Slow Mode In Slow mode, the oscillator frequency can be divided by a value defined in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage. 4.4.3 Wait Mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. All peripherals remain active. During Wait mode, the I bit (CC Register) is cleared, so as to enable all interrupts. All other registers and memory remain unchanged. The MCU will remain in Wait mode until an Interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the Interrupt or Reset Service Routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 17 below.
Figure 17. WAIT Flow Chart
WFI INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON OFF CLEARED
N RESET N INTERRUPT
Y
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON ON SET
4096 CPU CLOCK CYCLES DELAY
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON ON SET
FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 4.4.4 Halt Mode The Halt mode is the MCU lowest power consumption mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. The Halt mode cannot be used when the watchdog is enabled, if the HALT instruction is executed while the watchdog system is enabled, a watchdog reset is generated thus resetting the entire MCU. When entering Halt mode, the I bit in the CC Register is cleared so as to enable External Interrupts. If an interrupt occurs, the CPU becomes active. The MCU can exit the Halt mode upon reception of an interrupt or a reset. Refer to the Interrupt Mapping Table. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.
Figure 18. HALT Flow Chart
HALT INSTRUCTION
WATCHDOG RESET
Y
WDG ENABLED?
N OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT OFF OFF OFF CLEARED
N RESET N EXTERNAL INTERRUPT1) Y OSCILLATOR PERIPH. CLOCK2) CPU CLOCK I-BIT ON OFF ON SET Y
4096 CPU CLOCK CYCLES DELAY
OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT
ON ON ON SET
FETCH RESET VECTOR OR SERVICE INTERRUPT 1) or some specific interrupts 2) if reset PERIPH. CLOCK = ON ; if interrupt PERIPH. CLOCK = OFF Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.
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4.5 MISCELLANEOUS REGISTER The Miscellaneous register allows to select the SLOW operating mode, the polarity of external interrupt requests and to output the internal clock. Register Address: 0020h -- Read /Write Reset Value: 0000 0000 (00h)
7 PEI3 PEI2 MCO PEI1 PEI0 0 SMS
Bit 4:3 = PEI[1:0] External Interrupt EI0 Polarity Option. These bits are set and cleared by software. They determine which event on EI0 causes the external interrupt according to Table 9. Table 9. EI0 External Interrupt Polarity Options
MODE Falling edge and low level (Reset state) Falling edge only Rising edge only Rising and falling edge PEI1 0 1 0 1 PEI0 0 0 1 1
Bit 7:6 = PEI[3:2] External Interrupt EI1 Polarity Option. These bits are set and cleared by software. They determine which event on EI1 causes the external interrupt according to Table 8. Table 8. EI1 External Interrupt Polarity Options
MODE Falling edge and low level (Reset state) Falling edge only Rising edge only Rising and falling edge PEI3 0 1 0 1 PEI2 0 0 1 1
Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vector. Bit 1:2 = Unused, always read at 0. Warning: Software must write 1 to these bits for compatibility with future products. Bit 0 = SMS Slow Mode Select This bit is set and cleared by software. 0- Normal mode - fCPU = Oscillator frequency / 2 (Reset state) 1- Slow mode - fCPU = Oscillator frequency /32
Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vector. Bit 5 = MCO Main Clock Out This bit is set and cleared by software. When set, it enables the output of the Internal Clock on the PC2 I/O port. 0 - PC2 is a general purpose I/O port. 1 - MCO alternate function (fCPU is output on PC2 pin).
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5 ON-CHIP PERIPHERALS
5.1 I/O PORTS 5.1.1 Introduction The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - analog signal input (ADC) - alternate signal input/output for the on-chip peripherals. - external interrupt generation An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 5.1.2 Functional Description Each port is associated to 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and some of them to an optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, for specific ports which do not provide this register refer to the I/O Port Implementation Section 5.1.3. The generic I/O block diagram is shown on Figure 20. 5.1.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. All the inputs are triggered by a Schmitt trigger. 2. When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt polarity is given independently according to the description mentioned in the Miscellaneous register or in the interrupt register (where available). Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If several input pins are configured as inputs to the same interrupt vector, their signals are logically ANDed before entering the edge/level detection block. For this reason if one of the interrupt pins is tied low, it masks the other ones. 5.1.2.2 Output Mode The pin is configured in output mode by setting the corresponding DDR register bit. In this mode, writing "0" or "1" to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Note: In this mode, the interrupt function is disabled. 5.1.2.3 Digital Alternate Function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin's state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
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I/O PORTS (Cont'd) 5.1.2.4 Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. Warning: The analog input voltage level must be within the limits stated in the Absolute Maximum Ratings.
5.1.3 I/O Port Implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input (see Figure 20) or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 19. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
Figure 19. Recommended I/O State Transition Diagram
INPUT with interrupt
INPUT no interrupt
OUTPUT open-drain
OUTPUT push-pull
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I/O PORTS (Cont'd) Figure 20. I/O Block Diagram
ALTERNATE ENABLE ALTERNATE 1 M OUTPUT U X 0 VDD P-BUFFER (SEE TABLE BELOW) PULL-UP VDD DIODE (SEE TABLE BELOW) PAD ANALOG ENABLE (ADC) ANALOG SWITCH (SEE NOTE BELOW) DDR SEL N-BUFFER DR SEL 1 0 ALTERNATE INPUT ALTERNATE ENABLE GND
DR LATCH DATA BUS COMMON ANALOG RAIL DDR LATCH OR LATCH (SEE TABLE BELOW)
ALTERNATE ENABLE PULL-UP CONDITION
OR SEL
M U X
GND
CMOS EXTERNAL INTERRUPT SOURCE (EIx) POLARITY SEL FROM OTHER BITS SCHMITT TRIGGER
Table 10. Port Mode Configuration
Configuration Mode Floating Pull-up Push-pull True Open Drain Open Drain (logic level) Legend: 0present, not activated 1present and activated Pull-up 0 1 0 not present 0 P-buffer 0 0 1 not present 0 VDD Diode 1 1 1 not present in OTP and EPROM devices 1
Notes: - No OR Register on some ports (see register map). - ADC Switch on ports with analog alternate functions.
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Table 11. Port Configuration
Input (DDR = 0) Port Port A Port B Port C Pin Name OR = 0 PA0:PA7 PB0:PB7 PC0:PC5 Floating* Floating* Floating* OR = 1 Floating with Interrupt Pull-up with Interrupt Pull-up with Interrupt OR = 0 True Open Drain, High Sink Capability Open Drain (Logic level) Open Drain (Logic level) OR = 1 Reserved Push-pull Push-pull Output (DDR = 1)
*Reset State
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I/O PORTS (Cont'd) 5.1.4 Register Description 5.1.4.1 Data registers Port A Data Register (PADR) Port B Data Register (PBDR) Port C Data Register (PCDR) Read /Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
5.1.4.3 Option registers Port A Option Register (PAOR) Port B Option Register (PBOR) Port C Option Register (PCOR) Read/Write Reset Value: 0000 0000 (00h) (no interrupt)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bit 7:0 = D7-D0 Data Register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken in account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). 5.1.4.2 Data direction registers Port A Data Direction Register (PADDR) Port B Data Direction Register (PBDDR) Port C Data Direction Register (PCDDR) Read/Write Reset Value: 0000 0000 (00h) (input mode)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bit 7:0 = O7-O0 Option Register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allow to distinguish: in input mode if the interrupt capability or the floating configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: input interrupt with or without pull-up Output mode (only for PB0:PB7, PC0:PC5): 0: output open drain (with P-Buffer inactivated) 1: output push-pull Output mode (only for PA0:PA7): 0: output open drain 1: reserved
Bit 7:0 = DD7-DD0 Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 12. I/O Port Register Map and Reset Values
Address (Hex.) 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah Register Label PCDR Reset Value PCDDR Reset Value PCOR Reset Value PBDR Reset Value PBDDR Reset Value PBOR Reset Value PADR Reset Value PADDR Reset Value PAOR Reset Value 7 D7 0 DD7 0 O7 0 D7 0 DD7 0 O7 0 D7 0 DD7 0 O7 0 6 D6 0 DD6 0 O6 0 D6 0 DD6 0 O6 0 D6 0 DD6 0 O6 0 5 D5 0 DD5 0 O5 0 D5 0 DD5 0 O5 0 D5 0 DD5 0 O5 0 4 D4 0 DD4 0 O4 0 D4 0 DD4 0 O4 0 D4 0 DD4 0 O4 0 3 D37 0 DD3 0 O3 0 D37 0 DD3 0 O3 0 D37 0 DD3 0 O3 0 2 D2 0 DD2 0 O2 0 D2 0 DD2 0 O2 0 D2 0 DD2 0 O2 0 1 D1 0 DD1 0 O1 0 D1 0 DD1 0 O1 0 D1 0 DD1 0 O1 0 0 D0 0 DD0 0 O0 0 D0 0 DD0 0 O0 0 D0 0 DD0 0 O0 0
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5.2 WATCHDOG TIMER (WDG) 5.2.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. Figure 21. Watchdog Block Diagram 5.2.2 Main Features s Programmable timer (64 increments of 12288 CPU cycles) s Programmable reset s Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero
RESET
WATCHDOG CONTROL REGISTER (CR) WDGA T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER /12288
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WATCHDOG TIMER (Cont'd) 5.2.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 12,288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 1): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 13. Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 98.304 1.536
5.2.4 Low Power Modes Mode WAIT HALT Description No effect on Watchdog. Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set).
5.2.5 Interrupts None. 5.2.6 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset.
Table 14. Watchdog Timer Register Map and Reset Values
Address (Hex.) 0024h Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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5.3 16-BIT TIMER 5.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 5.3.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s Output compare functions with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Input capture functions with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Pulse Width Modulation mode (PWM) s One Pulse mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 1. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 5.3.3 Functional Description 5.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 1. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 22. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE
8 high
8 low
8-bit buffer
8 high low
8 high
8 low
8 high
8 low
8 high
8 low
8
EXEDG
16
1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2
16
16
16
CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1 pin
6
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register).
Beginning of the sequence
At t0 Read MS Byte Other instructions Read At t0 +t LS Byte
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 5.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont'd) Figure 23. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 24. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 25. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
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16-BIT TIMER (Cont'd) 5.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR
The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 1). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as a floating input).
When an input capture occurs: - The ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 6). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure 26. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 27. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 5.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCIE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
fCPU
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 1)
If the timer clock is an external clock, the formula is:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 1). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 8). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 9). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 28. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in either One-Pulse mode or PWM mode.
16 BIT FREE RUNNING COUNTER
OC1E OC2E
CC1
CC0
16-bit
OUTPUT COMPARE CIRCUIT
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
16-bit
16-bit
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 29. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 30. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 5.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 1).
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 10). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.
One Pulse mode cycle
When event occurs on ICAP1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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16-BIT TIMER (Cont'd) Figure 31. One Pulse Mode Timing Example
COUNTER ICAP1 OCMP1
FFFC FFFD FFFE
2ED0 2ED1 2ED2 2ED3
FFFC FFFD
OLVL2
OLVL1
OLVL2
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 32. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1
2ED0 2ED1 2ED2
34E2
FFFC
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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16-BIT TIMER (Cont'd) 5.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 1). If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 11) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.
Pulse Width Modulation cycle
When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
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16-BIT TIMER (Cont'd) 5.3.4 Low Power Modes
Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
5.3.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 5.3.6 Summary of Timer modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM Mode
1) 2)
Input Capture 1 Yes Yes No No
AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes 1) No Partially 2) Not Recommended 3) Not Recommended No No
See note 4 in Section 0.1.3.5 One Pulse Mode See note 5 in Section 0.1.3.5 One Pulse Mode 3) See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode
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16-BIT TIMER (Cont'd) 5.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 15. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 0 0 0 0
INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 16. 16-Bit Timer Register Map and Reset Values
Address (Hex.) Register Name 7 ICIE 0 OC1E 0 ICF1 0 MSB MSB MSB 1 MSB 0 MSB 1 MSB 0 MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB 6 OCIE 0 OC2E 0 OCF1 0 0 0 0 0 1 1 1 1 5 TOIE 0 OPM 0 TOF 0 0 0 0 0 1 1 1 1 4 FOLV2 0 PWM 0 ICF2 0 0 0 0 0 1 1 1 1 3 FOLV1 0 CC1 0 OCF2 0 0 0 0 0 1 1 1 1 2 OLVL2 0 CC0 0 0 0 0 0 0 1 1 1 1 1 IEDG1 0 IEDG2 0 0 0 0 0 0 1 0 1 0 0 OLVL1 0 EXEDG 0 0 LSB LSB LSB 0 LSB 0 LSB 0 LSB 0 LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB -
TimerA: 32 CR1 TimerB: 42 Reset Value TimerA: 31 CR2 TimerB: 41 Reset Value TimerA: 33 SR TimerB: 43 Reset Value TimerA: 34 IC1HR TimerB: 44 Reset Value TimerA: 35 IC1LR TimerB: 45 Reset Value TimerA: 36 OC1HR TimerB: 46 Reset Value TimerA: 37 OC1LR TimerB: 47 Reset Value TimerA: 3E OC2HR TimerB: 4E Reset Value TimerA: 3F OC2LR TimerB: 4F Reset Value TimerA: 38 CHR TimerB: 48 Reset Value TimerA: 39 CLR TimerB: 49 Reset Value TimerA: 3A ACHR TimerB: 4A Reset Value TimerA: 3B ACLR TimerB: 4B Reset Value TimerA: 3C IC2HR TimerB: 4C Reset Value TimerA: 3D IC2LR TimerB: 4D Reset Value
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5.4 SERIAL PERIPHERAL INTERFACE (SPI) 5.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller. Refer to the Pin Description chapter for the devicespecific pin-out. 5.4.2 Main Features s Full duplex, three-wire synchronous transfers s Master or slave operation s Four master mode frequencies s Maximum slave mode frequency = fCPU/2. s Four programmable master bit rates s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision flag protection s Master mode fault protection capability. 5.4.3 General description The SPI is connected to external devices through 4 alternate pins: - MISO: Master In Slave Out pin - MOSI: Master Out Slave In pin - SCK: Serial Clock pin - SS: Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 1. The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete. Four possible data/clock timing relationships may be chosen (see Figure 4) but master and slave must be programmed with the same timing mode.
Figure 33. Serial Peripheral Interface Master/Slave
MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK
SCK +5V
SS
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 34. Serial Peripheral Interface Block Diagram
Internal Bus Read Read Buffer
DR IT request
MOSI MISO
8-Bit Shift Register
SPIF WCOL - MODF -
SR
-
Write SPI STATE CONTROL
SCK SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL
SERIAL CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) 5.4.4 Functional Description Figure 1 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: - A Control Register (CR) - A Status Register (SR) - A Data Register (DR) Refer to the CR, SR and DR registers in Section 0.1.7 for the bit definitions. 5.4.4.1 Master Configuration In a master configuration, the serial clock is generated on the SCK pin. Procedure - Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register). - Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 4). - The SS pin must be connected to a high level signal during the complete byte transmit sequence. - The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a high level signal).
In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is written the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 5.4.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure - For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 4. - The SS pin must be connected to a low level signal during the complete byte transmit sequence. - Clear the MSTR bit and set the SPE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2.A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 0.1.4.6 ). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 0.1.4.4 ).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 5.4.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer. Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes. The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge. Figure 4, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. The SS pin is the slave device select input and can be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge. CPHA bit is set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition. No write collision should occur even if the SS pin stays low during a transfer of several bytes (see Figure 3). CPHA bit is reset The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition. The SS pin must be toggled high and low between each byte transmitted (see Figure 3). To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision.
Figure 35. CPHA / SS Timing Diagram
MOSI/MISO Master SS Slave SS (CPHA=0) Slave SS (CPHA=1)
Byte 1
Byte 2
Byte 3
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 36. Data Clock Timing Diagram
CPHA =1
SCLK (with CPOL = 1) SCLK (with CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
CPOL = 1
CPOL = 0
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
VR02131B
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SERIAL PERIPHERAL INTERFACE (Cont'd) 5.4.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. In Slave mode When the CPHA bit is set: The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the external MISO pin of the slave device. The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.
When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low. For this reason, the SS pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision. In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer. The SS pin signal must be always high on the master device. WCOL bit The WCOL bit in the SR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 5).
Figure 37. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SR OR
THEN
Read SR
THEN
2nd Step
Read DR
SPIF =0 WCOL=0
Write DR
SPIF =0 WCOL=0 if no transfer has started WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SR
THEN
2nd Step
Read DR
WCOL=0
Note: Writing in DR register instead of reading in it do not reset WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 5.4.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: - The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. 5.4.4.6 Overrun Condition An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripheral.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 5.4.4.7 Single Master and Multimaster Configurations For more security, the slave device may respond There are two types of SPI systems: to the master with the received data byte. Then the - Single Master System master will receive the previous byte back from the - Multimaster System slave device if all MISO and MOSI pins are connected and the slave has not written its DR register. Single Master System Other transmission security methods can use A typical single master system may be configured, ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as mand fields. slaves (see Figure 6). Multi-master System The master device selects the individual slave deA multi-master system may also be configured by vices by using four pins of a parallel port to control the user. Transfer of master control could be imthe four SS pins of the slave devices. plemented using a handshake method through the The SS pins are pulled high during reset since the I/O ports or by an exchange of code messages master device ports will be forced to be inputs at through the serial peripheral interface system. that time, thus disabling the slave devices. The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit Note: To prevent a bus conflict on the MISO line in the SR register. the master allows only one active slave device during a transmission. Figure 38. Single Master Configuration
SS SCK Slave MCU MOSI MISO SCK Slave MCU
SS SCK Slave MCU
SS SCK Slave MCU
SS
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO SCK Master MCU 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 5.4.5 Low Power Modes
Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
5.4.6 Interrupts
Interrupt Event SPI End of Transfer Event Master Mode Fault Event Event Flag SPIF MODF Enable Control Bit SPIE Exit from Wait Yes Yes Exit from Halt No No
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 5.4.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh)
7
SPIE SPE SPR2 MSTR CPOL CPHA SPR1
0
SPR0
Bit 3 = CPOL Clock polarity. This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Bit 1:0 = SPR[1:0] Serial peripheral rate. These bits are set and cleared by software.Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. These 2 bits have no effect in slave mode. Table 17. Serial Peripheral Baud Rate
Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1
Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register Bit 6 = SPE Serial peripheral output enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 0.1.4.5 Master Mode Fault). 0: I/O port connected to pins 1: SPI alternate functions connected to pins The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 1. 0: Divider by 2 enabled 1: Divider by 2 disabled Bit 4 = MSTR Master. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 0.1.4.5 Master Mode Fault). 0: Slave mode is selected 1: Master mode is selected, the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
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SERIAL PERIPHERAL INTERFACE (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h)
7 SPIF WCOL MODF 0 -
DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been approved by a clearing sequence. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 5). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 0.1.4.5 Master Mode Fault). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused.
The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A write to the the DR register returns the value located in the buffer and not the contents of the shift register (See Figure 2 ).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table 18. SPI Register Map and Reset Values
Address (Hex.) 21 22 23 Register Name DR Reset Value CR Reset Value SR Reset Value 7 D7 x SPIE 0 SPIF 0 6 D6 x SPE 0 WCOL 0 5 D5 x SPR2 0 0 4 D4 x MSTR 0 MODF 0 3 D3 x CPOL x 0 2 D2 x CPHA x 0 1 D1 x SPR1 x 0 0 D0 x SPR0 x 0
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5.5 8-BIT A/D CONVERTER (ADC) 5.5.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 5.5.2 Main Features s 8-bit conversion s Up to 8 channels with multiplexed input s Linear successive approximation s Data register (DR) which contains the results s Conversion complete status flag s On/Off bit (to reduce consumption) The block diagram is shown in Figure 1.
Figure 39. ADC Block Diagram
COCO
-
ADON
0
-
CH2
CH1
CH0
(Control Status Register) CSR AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
ANALOG MUX
SAMPLE & HOLD
ANALOG TO DIGITAL CONVERTER
fCPU
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
(Data Register) DR
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8-BIT A/D CONVERTER (ADC) (Cont'd) 5.5.3 Functional Description The high level reference voltage VDDA must be connected externally to the V DD pin. The low level reference voltage V SSA must be connected externally to the VSS pin. In some devices (refer to device pin out description) high and low level reference voltages are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. Figure 40. Recommended Ext. Connections
VDD
0.1F
VDDA VSSA
ST7
RAIN VAIN Px.x/AINx
Characteristics: The conversion is monotonic, meaning the result never decreases if the analog input does not and never increases if the analog input does not. If input voltage is greater than or equal to VDD (voltage reference high) then results = FFh (full scale) without overflow indication. If input voltage VSS (voltage reference low) then the results = 00h. The conversion time is 64 CPU clock cycles including a sampling time of 31.5 CPU clock cycles. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. The A/D converter is linear and the digital result of the conversion is given by the formula: 255 x Input Voltage Digital result = Reference Voltage Where Reference Voltage is VDD - VSS.
The accuracy of the conversion is described in the Electrical Characteristics Section. Procedure: Refer to the CSR and DR register description section for the bit definitions. Each analog input pin must be configured as input, no pull-up, no interrupt. Refer to the "I/O Ports" chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: - Select the CH2 to CH0 bits to assign the analog channel to convert. Refer to Table 1. - Set the ADON bit. Then the A/D converter is enabled after a stabilization time (typically 30 s). It then performs a continuous conversion of the selected channel. When a conversion is complete - The COCO bit is set by hardware. - No interrupt is generated. - The result is in the DR register. A write to the CSR register aborts the current conversion, resets the COCO bit and starts a new conversion. 5.5.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed. Mode WAIT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
HALT
5.5.5 Interrupts None.
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8-BIT A/D CONVERTER (ADC) (Cont'd) 5.5.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h)
7 COCO ADON 0 CH2 CH1 0 CH0
These bits are set and cleared by software. They select the analog input to convert. Table 19. Channel Selection Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1
Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete. 1: Conversion can be read from the DR register. Bit 6 = Reserved. Must always be cleared. Bit 5 = ADON A/D converter On This bit is set and cleared by software. 0: A/D converter is switched off. 1: A/D converter is switched on. Note: A typical 30 s delay time is necessary for the ADC to stabilize when the ADON bit is set. Bit 4 = Reserved. Forced by hardware to 0. Bit 3 = Reserved. Must always be cleared. Bits 2:0: CH[2:0] Channel Selection
*IMPORTANT NOTE: The number of pins AND the channel selection vary according to the device. REFER TO THE DEVICE PINOUT).
DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h)
7 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 AD0
Bit 7:0 = AD[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Reading this register resets the COCO flag.
Table 20. ADC Register Map
Address (Hex.) 70 Reset Value 71 Reset Value Register Name DR CSR 7 AD7 0 COCO 0 6 AD6 0 0 5 AD5 0 ADON 0 4 AD4 0 0 0 3 AD3 0 0 2 AD2 0 CH2 0 1 AD1 0 CH1 0 0 AD0 0 CH0 0
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6 INSTRUCTION SET
6.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do Table 21. ST7 Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination/ Source
Pointer Address (Hex.)
Pointer Size (Hex.) +0 +1
Length (Bytes)
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC-128/PC+127 00..FF 00..FF 00..FF 00..FF byte 00..FF byte
1)
+1 +2 + 0 (with X register) + 1 (with Y register) +1 +2 00..FF 00..FF 00..FF 00..FF 00..FF byte word byte word byte +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
PC-128/PC+1271)
btjt [$10],#7,skip 00..FF
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (Cont'd) 6.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
6.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 6.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 6.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
6.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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ST7 ADDRESSING MODES (Cont'd) 6.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 22. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Addition/subtraction operations Bit Compare Function
SWAP CALL, JP
Swap Nibbles Call or Jump subroutine
6.1.7 Relative Mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.
Available Relative Direct/ Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC Clear
Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations
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6.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Code Condition Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION GROUPS (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. interrupt = 1 Jump if ext. interrupt = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) H=1? H=0? I=1? I=0? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > jrf * Pop CC, A, X, PC inc X jp [TBL.w] reg, M H tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 0 I N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst M M M M Src H H H I N N N N N Z Z Z Z Z C C C
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INSTRUCTION GROUPS (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack A=A+M pop reg pop CC PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I=0 C <= Dst <= C C => Dst => C S = Max allowed A=A-M-C C=1 I=1 C <= Dst <= 0 C <= Dst <= 0 0 => Dst => C Dst7 => Dst => C A=A-M reg, M reg, M reg, M reg, M A M 1 N N 0 N N N N 1 0 N Z Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 0 N N Z Z C C push Y C=0 A reg CC M M M M reg, CC 0 H I N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src H I N Z C
Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt
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7 ELECTRICAL CHARACTERISTICS
7.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that VI and VO be higher than V SS and lower than V DD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD or V SS). Power Considerations.The average chip-junction temperature, TJ, in Celsius can be obtained from: TJ= TA + PD x RthJA Where: TA = Ambient Temperature. RthJA = Package thermal resistance (junction-to ambient). PD = PINT + P PORT. PINT = IDD x VDD (chip internal power). PPORT =Port power dissipation determined by the user)
Value -0.3 to 6.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 80 80 150 -60 to 150 Unit V V V V mA mA C C
Symbol VDD VI VAI VO IVDD IVSS TJ TSTG Supply Voltage Input Voltage
Parameter
Analog Input Voltage (A/D Converter) Output Voltage Total Current into VDD (source) Total Current out of VSS (sink) Junction Temperature Storage Temperature
Note: Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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7.2 RECOMMENDED OPERATING CONDITIONS
Value Symbol Parameter Test Conditions Min. 1 Suffix Version TA Operating Temperature 6 Suffix Version 3 Suffix Version VDD fOSC Operating Supply Voltage Oscillator Frequency fOSC = 16 MHz (1 & 6 Suffix) fOSC = 8 MHz VDD = 3.0V VDD = 3.5V (1 & 6 Suffix) 0 -40 -40 3.5 3.0 01) 01) Typ. Max. 70 85 125 5.5 5.5 8 16 C C C V MHz Unit
Note 1: A/D operation and Oscillator start-up are not guaranteed below 1MHz.
Figure 41. Maximum Operating Frequency (f OSC) Versus Supply Voltage (VDD)
FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY GUARANTEED IN THIS AREA
fOSC
[MHz]
FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURE HIGHER THAN 85C
16
8
4 1 0 2.5 3 3.5 4 4.5 5 5.5
Supplly Voltage [V]
FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR
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7.3 DC ELECTRICAL CHARACTERISTICS (TA = -40C to +125C and VDD = 5V unless otherwise specified)
Value Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIL VIH VHYS
Input Low Level Voltage All Input pins Input High Level Voltage All Input pins Hysteresis Voltage 1) All Input pins Low Level Output Voltage All Output pins Low Level Output Voltage High Sink I/O pins High Level Output Voltage All Output pins Input Leakage Current All Input pins but RESET 4) Input Leakage Current RESET pin Reset Weak Pull-up RON
3V < VDD < 5.5V 3V < VDD < 5.5V VDD x 0.7 400 IOL = +10A IOL = + 2mA IOL = +10A IOL = +10mA IOL = + 15mA IOL = + 20mA, TA = 85C max IOH = - 10A IOH = - 2mA VIN = VSS (No Pull-up configured) VIN = VDD VIN = VDD 20 60
VDD x 0.3
V V mV
VOL
0.1 0.4 0.1 1.5 3.0 3.0 4.9 4.2 0.1 0.1 40 120 100 3 5.5 10 1.5 2.5 4 2 3.5 6 0.8 1 1.6 1 5 1.0
V
VOH IIL IIH IIH RON RPU
V
A 1.0 80 240 6 11 20 3 5 8 4 7 12 1.5 2 3.5 10 20 k k mA
IDD
VIN > VIH VIN < VIL I/O Weak Pull-up RPU VIN < VIL fOSC = 4 MHz, fCPU = 2 MHz Supply Current in fOSC = 8 MHz, fCPU = 4 MHz 2) RUN Mode fOSC = 16 MHz, fCPU = 8 MHz fOSC = 4 MHz, fCPU= 125 kHz Supply Current in SLOW Mode 2) fOSC = 8 MHz, fCPU= 250 kHz fOSC = 16 MHz, fCPU= 500 kHz fOSC = 4MHz, fCPU = 2MHz Supply Current in WAIT Mode 3) fOSC = 8MHz, fCPU = 4 MHz fOSC = 16MHz, fCPU = 8 MHz fOSC = 4 MHz, fCPU= 125 kHz Supply Current in WAIT-MINIfOSC = 8 MHz, fCPU= 250 kHz MUM Mode5) fOSC = 16 MHz, fCPU= 500 kHz ILOAD = 0mA, TA = 85C max Supply Current in HALT Mode ILOAD = 0mA
mA
mA
mA A
Notes: 1. Hysteresis voltage between switching levels. Based on characterisation results, not tested. 2. CPU running with memory access, no DC load or activity on I/O's; clock input (OSCIN) driven by external square wave. 3. No DC load or activity on I/O's; clock input (OSCIN) driven by external square wave. 4. Except OSCIN and OSCOUT 5. WAIT Mode with SLOW Mode selected. Based on characterisation results, not tested.
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7.4 RESET CHARACTERISTICS (TA=-40...+125oC and V DD=5V10% unless otherwise specified.
Symbol RON tRESET tPULSE Parameter Reset Weak Pull-up RON Pulse duration generated by watchdog and POR reset Minimum pulse duration to be applied on external RESET pin Conditions VIN > VIH VIN < VIL Min 20 60 Typ 1) 40 120 1 10 1) Max 80 240 Unit k s ns
Note: 1) These values given only as design guidelines and are not tested. 7.5 OSCILLATOR CHARACTERISTICS (TA = -40C to +125C unless otherwise specified)
Value Symbol gm fOSC tSTART Parameter Oscillator transconductance Crystal frequency Osc. start up time Test Conditions Min. 2 1 VDD = 5V10% Typ. Max. 9 16 50 mA/V MHz ms Unit
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7.6 A/D CONVERTER CHARACTERISTICS (ST72212 and ST72213 only) (TA = -40C to +125C and VDD = 5V10% unless otherwise specified )
Symbol TSAMPLE Res DLE ILE VAIN IADC tSTAB tCONV RAIN CHOLD RSS Parameter Sample Duration ADC Resolution Differential Linearity Error* Integral Linearity Error* Analog Input Voltage Supply current rise during A/D conversion Stabilization time after ADC enable Conversion Time Resistance of analog sources (VAIN) Hold Capacitance Resistance of sampling switch and internal trace fCPU=8MHz, T=25C, VDD=VDDA=5V fCPU=8MHz VDD=VDDA=5V VSSA 1 30 8 64 15 22 2 fCPU=8MHz VDD=VDDA=5V Conditions Min Typ 31.5 8 0.6 1 2 VDDA V mA s s 1/fCPU pF Max Unit 1/fCPU bit
*Note: ADC Accuracy vs. Negative Injection Current: For Iinj-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB by 10K increase of the external analog source impedance. These measurement results and recommendations take worst case injection conditions into account: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature.
VDD RAIN VAIN Px.x/AINx Cpin 5pF VT = 0.6V SS VT = 0.6V
Sampling Switch
RSS 2 Chold 22 pF
Cpin VT SS Chold
= input capacitance = threshold voltage = sampling switch
leakage max. 1A VSS
= sample/hold capacitance leakage = leakage current at the pin due to various junctions
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A/D CONVERTER CHARACTERISTICS (Cont'd) Figure 42. ADC conversion characteristics
Offset Error OSE 255 254 253 252 251 250 ( 2) code out 7 ( 1) 6 5 4 3 2 1 0 1 2 3 4 5 6 7 250 251 252 253 254 255 256 Vin(A) (LSBideal)
VR02133A
Gain Error GE
1LSB
ideal
V -V refP refM = --------------------------------------256
(5) (4) (3) 1 LSB (ideal)
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DLE) (4) Integral non-linearity error (ILE) (5) Center of a step of the actual transfer curve
Offset Error OSE
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ST72101/ST72212/ST72213
7.7 SPI CHARACTERISTICS
Serial Peripheral Interface Value Ref. Symbol Parameter Master Slave Master Slave Slave Slave Master Slave Master Slave Master Slave Master Slave Condition Min. fSPI 1 2 3 4 5 6 7 8 9 10 11 12 13 tSPI tLead tLag tSPI_H tSPI_L tSU tH tA tDis tV tHold tRise tFall SPI frequency SPI clock period Enable lead time Enable lag time Clock (SCK) high time Clock (SCK) low time Data set-up time Data hold time (inputs) Access time (time to data active from high impedance state) Disable time (hold time to high impedance state) Data valid Data hold time (outputs) 1/128 dc 4 2 120 120 100 90 100 90 100 100 100 100 0 Slave 240 Master (before capture edge) Slave (after enable edge) Master (before capture edge) Slave (after enable edge) 0.25 120 0.25 0 100 100 100 100 ns tCPU ns tCPU ns ns s ns s 120 Max. 1/4 1/2 fCPU tCPU ns ns ns ns ns ns ns Unit
Rise time Outputs: SCK,MOSI,MISO (20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS Fall time Outputs: SCK,MOSI,MISO (70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
Measurement points are V OL, VOH, VIL and VIH in the SPI Timing Diagram Figure 43. SPI Master Timing Diagram CPHA=0, CPOL=0
SS (INPUT) SCK (OUTPUT) 4 MISO (INPUT) MOSI (OUTPUT) 6 D7-IN 7 D7-OUT 11 1
13
12
5 D6-IN D6-OUT D0-IN D0-OUT VR000109
10
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SPI CHARACTERISTICS (Cont'd) Measurement points are V OL, VOH, VIL and VIH in the SPI Timing Diagram Figure 44. SPI Master Timing Diagram CPHA=0, CPOL=1
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 13 5 6 10 D7-IN 7 D7-OUT 11 4 D6-IN D6-OUT D0-IN D0-OUT VR000110 12
Figure 45. SPI Master Timing Diagram CPHA=1, CPOL=0
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 13 4 6 10 7 D7-IN 11 D6-IN D0-IN VR000107 5 D7-OUT D6-OUT D0-OUT 12
Figure 46. SPI Master Timing Diagram CPHA=1, CPOL=1
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 12 5 6 10 4 D7-IN 7 D7-OUT 11 D6-IN D6-OUT D0-IN D0-OUT VR000108 13
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SPI CHARACTERISTICS (Cont'd) Measurement points are V OL, VOH, VIL and VIH in the SPI Timing Diagram Figure 47. SPI Slave Timing Diagram CPHA=0, CPOL=0
SS (INPUT) SCK (INPUT) MISO HIGH-Z (OUTPUT) 8 MOSI (INPUT) 6 2 1 13 4 D7-OUT 10 D7-IN 7 VR000113 D6-IN 5 D6-OUT 11 D0-IN D0-OUT 9 12 3
Figure 48. SPI Slave Timing Diagram CPHA=0, CPOL=1
SS (INPUT) SCK (INPUT) HIGH-Z MISO (OUTPUT) 8 MOSI (INPUT) 6 2 1 12 5 D7-OUT 10 D7-IN 7 VR000114 D6-IN 4 D6-OUT 11 D0-IN D0-OUT 9
13
3
Figure 49. SPI Slave Timing Diagram CPHA=1, CPOL=0
SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) MOSI (INPUT) 8 D7-IN 6 7 VR000111 4 5 D7-OUT 10 D6-IN D6-OUT 11 D0-IN D0-OUT 9 1 13 12 3
Figure 50. SPI Slave Timing Diagram CPHA=1, CPOL=1
SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) MOSI (INPUT) 8 D7-IN 6 7 VR000112 5 4 D7-OUT 10 D6-IN D6-OUT 11 D0-IN D0-OUT 9 1 12 13 3
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8 GENERAL INFORMATION
8.1 EPROM ERASURE EPROM version devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents. An Ultraviolet source of wave length 2537 A yielding a total integrated dosage of 15 Watt-sec/cm2 is required to erase the device. It will be erased in 15 to 20 minutes if such a UV lamp with a 12mW/cm2 power rating is placed 1 inch from the device window without any interposed filters.
8.2 PACKAGE MECHANICAL DATA Figure 51. 28-Pin Plastic Small Outline Package, 300-mil Width
Dim.
D L L A1 A a B e C h x 45x
mm Min 2.35 0.10 0.33 0.23 17.70 7.40 1.27 10.00 0.25 0 0.40 10.65 0.394 0.75 0.010 8 0 1.27 0.016 Typ Max Min 2.65 0.093 0.30 0.004 0.51 0.013 0.32 0.009 18.10 0.697 7.60 0.291
inches Typ Max 0.104 0.012 0.020 0.013 0.713 0.299 0.050 0.419 0.030 8 0.050
A A1 B C D E e H h
EH
L N
Number of Pins 28
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Figure 52. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
mm Min 3.56 0.51 3.05 0.36 0.76 0.20 27.43 7.62 Typ Max Min 0.020 3.56 4.57 0.120 0.140 0.180 0.46 0.58 0.014 0.018 0.023 1.02 1.40 0.030 0.040 0.055 0.25 0.36 0.008 0.010 0.014 28.45 1.080 1.100 1.120 8.89 9.40 0.300 0.350 0.370 1.78 10.16 12.70 1.40 2.54 Number of Pins N 32 0.070 0.400 0.500 0.055 inches Typ Max
Dim.
E eC
A
A2 A
3.76 5.08 0.140 0.148 0.200
A1 A2 b
E1 C eA eB
A1
L
b1 C D E E1 e eA eB eC L
b2 D
b
e
9.91 10.41 11.05 0.390 0.410 0.435
3.05 3.81 0.100 0.120 0.150
Figure 53. 32-Pin Shrink Ceramic Dual In-Line Package
Dim. A A1 B B1 C D D1 E E1 e G G1 G2 L O CDIP32SW N 9.45 0.38 0.36 0.64 0.20 mm Min Typ Max 3.63 0.015 0.46 0.58 0.014 0.018 0.023 0.89 1.14 0.025 0.035 0.045 0.25 0.36 0.008 0.010 0.014 26.67 10.16 1.78 9.40 14.73 1.12 3.30 7.37 32 1.050 0.400 0.070 0.370 0.580 0.044 0.130 0.290 Min inches Typ Max 0.143
29.41 29.97 30.53 1.158 1.180 1.202
9.91 10.36 0.372 0.390 0.408
Number of Pins
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8.3 ORDERING INFORMATION Each device is available for production in user programmable version (OTP) as well as in factory coded version (ROM). OTP devices are shipped to customer with a default blank content FFh, while ROM factory coded parts contain the code sent by customer. There is one common EPROM version for debugging and prototyping which features the maximum memory size and peripherals of the family. Care must be taken to only use resources available on the target device. 8.3.1 Transfer Of Customer Code Customer code is made up of the ROM contents and the list of the selected options (if any). The Figure 54. ROM Factory Coded Device Types
TEMP. DEVICE PACKAGE RANGE / XXX Code name (defined by STMicroelectronics) 1 = standard 0 to +70C 3 = automotive -40 to +125C 6 = industrial -40 to +85C B = Plastic DIP M = Plastic SOIC ST72101G1 ST72101G2 ST72212G2 ST72213G1
ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19 format generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Figure 55. OTP User Programmable Device Types
TEMP. DEVICE PACKAGE RANGE
XXX Option (if any) 3 = automotive -40 to +125C 6 = industrial -40 to +85C B = Plastic DIP M = Plastic SOIC ST72T101G1 ST72T101G2 ST72T212G2 ST72T213G1
Note: The ST72E251G2D0 (CERDIP 25 C) is used as the EPROM version for the above devices.
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ST72101, ST72213 and ST72212 MICROCONTROLLER OPTION LIST
Customer Address
............................. ............................. ............................. Contact ............................. Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references Device: [ ] ST72101 [ ] ST72212 [ ] ST72213 Package: [ ] Dual in Line Plastic [ ] Small Outline Plastic with conditioning: [ ] Standard (Stick) [ ] Tape & Reel Temperature Range: [ ] 0C to + 70C [ ] - 40C to + 85C [ ] - 40C to + 125C Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ " Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: SDIP32: 10 SO28: 8
Comments: Supply Operating Range in the application: Oscillator Frequency in the application: Notes ............................. Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Date .............................
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9 SUMMARY OF CHANGES
Change Description (Rev. 1.5 to 1.6) Added new External Connections section Removed RP external resistor Changed ORed to ANDed in External interrupts paragraph, to read "If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed before entering the edge/level detection block". Added note "Any modification of one of these two bits resets the interrupt request related to this interrupt vector." Added clamping diodes to I/O pin figure and table Added sections on low power modes and interrupts to peripheral descriptions Changed 16-bit Timer Chapter Added details to description of FOLV1 and FOLV2 bits Added ADC recommended external connections Added Reset characteristics section Added figure to ADC electrical characteristics section Page 9 16 18 and 24
23 26 31,43,58,63 32 to 48 44 63 74 75
Change Description (Rev. 1.6 to 1.7) SPR2 bit reinstated in SPI chapter Change Description (Rev. 1.7 to 1.8) of 31 May 2001 SPI frequency changed from fCPU/2 to fCPU/4 in Table 17. 60 49 to 61
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2001 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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